A High-throughput Reconfigurable Viterbi Decoder

摘要：

A reconfigurable Viterbi decoder with high throughput and low complexity is presented in this paper. The proposed Viterbi decoder supports constraint lengths ranging from 3–9, code rates in the range of 1/2.1/3, and arbitrary truncation lengths. The decoder achieves a low bit error ratio in multiple standards, such as GPRS, WiMax, LTE, CDMA, and 3G. The proposed decoder is implemented on Xilinx XC5VLX330 device and the frequency achieved is 202 MHz with the throughput of 202 Mbps, which is apparently superior to the other current reconfigurable Viterbi decoders on the FPGA platform.

关键词： Decoder reconfigurable high-throughput FPGA.

作者: Rongchun Li Yong Dou Jie Zhou Guoqing Lei

作者单位: Computer School National University of Defense Technology (NUDT) Changsha, China Computer School National University of Defense Technology (NUDT)Changsha, China

会议类型: 国际会议

会议名称: 2011年无线通信与信号处理国际会议(WCSP 2011)

会议地点: 南京

会议语种:英文

页码: 1-6

在线出版日期: 2011-11-09（万方平台首次上网日期，不代表论文的发表时间）