Design of Resistant DPA Three-valued Counter Based on SABL

摘要：

Through studying the design principles of multivalued logic circuit and the SABL circuit, this paper presents a design scheme of three-valued counter. Two-valued coding method and SABL circuit characteristics such as complementary output signals and the capacitance coupling effect -are integrated to implement the developed scheme. Then, the current compensation circuit is used to keep steady output logic 1, and further to achieve n-bit three-valued counter. Finally, with the parameters of SMIC 0.13μm CMOS device, the SABL three-valued counter is simulated by SPECTRE. The results show that the designed circuit has correct logic function and constant power per clock cycle.

关键词： SABL DPA Three-valued counter Multi-valued logic.

作者: Yuejun Zhang Pengjun Wang Lipeng Hao

作者单位: Institute of Circuits and Systems, Ningbo University, Ningbo 315211, China Institute of Circuits and Systems, Ningbo University, Ningbo 315211, China State Key Laboratory of A

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 17-20

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）