High-parallel LDPC decoder with power gating design
Leakage power is growing comparable to dynamic power dissipation as a result of technology trends, and thus it has become an important issue in low-power circuit design. As a popular technique for standby power reduction, power gating is applied to highparallel LDPC decoder for WiMAX standard. The clustered-block processing engine (CBPE) array are divided into 9 power domains, and they are switched on or off according to different code lengths of LDPC code defined in WiMAX standard. As CBPE array occupies about 70％ of the decoder system, the dedicated power gating strategy is very effective in shorter code length case since more power domains can be switched off. At shortest code length, power gating design brings about 55％ power reduction compared to that of longest code length.
Ying Cui Xiao Peng Yu Jin Peilin Liu Shinji Kimura Satoshi Goto
Graduate School of Information, Production and Systems, Waseda University
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
29-32
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）