A Reconfigurable Macro-Pipelined DCT/IDCT Accelerator
In this paper, a reconfigurable macro-pipelined (RMP) accelerator is proposed to speed up the Discrete Cosine Transform (DCT) and Inverse Discrete Cosine Transform (IDCT). The accelerator can be reconfigured to compute fixed-point or floating-point, onedimensional or multi-dimensional DCT/IDCT according to different system requirements. The prototype is implemented on Xilinx ML605 experiment board with 64 PEs. It takes 64 cycles at 200MHz to complete an 8×8 2D DCT and gets a peak performance of 25.6 GFLOPS for the floating-point DCT. The excellent scalability of this architecture enables the accelerator to scale up to an extremely high performance.
Wenqi Bao Jiang Jiang Qing Sun Yuzhuo Fu
School of Microelectronics, Shanghai Jiao Tong University, Shanghai 200240, China Microelectronics Building, No.800, Dongchuan Road, Shanghai, China
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
33-36
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）