Saving 78.11％ Dhrystone power consumption in FPU by clock gating while still keeping co-operation with CPU
We have applied thoroughly clock gating technique to the SH-4A FPU (Floating Point Unit) core1 while still keeping it co-operates with CPU core. As a result, 97％ flip-flops in FPU is gated. And the power consumption is saved up to 78.11％ in FPU, corresponding to 17.02％ power consumption reducing of total CPU and FPU core in Dhrystone benchmark. This paper introduces such approach in which the clock is controlled thoroughly and provided to FPU only when the FPU instruction is under-processing.
Minh Thien Trieu Huong Thien Hoang Phong The Vo Hung Bao Vo Yoichi Yuyama
Renesas Design Vietnam Company Ltd., Ho Chi Minh City, Vietnam Renesas Electronic Corporation Tokyo, Japan
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
47-50
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）