A hardware/software co-design approach for multiple-standard video bitstream parsing

摘要：

In this paper, a hardware/software co-design approach is proposed to parse the video bitstream which conforms to various video compression standards. The layered structure of the syntax elements in video bitstreams is analyzed. Then a hardware/software partition is proposed accordingly. Due to the high data rate, syntax elements in slice data and lower layers are commonly parsed by hardware. As for syntax elements in slice header and upper layers, we proposed a hw/sw co-design approach in order to combine the advantage of hardware acceleration and software flexibility, specific hardware accelerators are designed to parse these codes. But the parsing process of these codes in slice header and upper layer is controlled by software instead of hardware Finite state machine (FSM). This approach can speed up the process of Variable-Length Decoding (VLD) while it still has the flexibility to support multiple video coding standards.

关键词： bitstream parsing fixed-length code Exponential Golomb code VLD

作者: Sha Shen Huibo Zhong Yibo Fan Xiaoyang Zeng

作者单位: The State key lab of ASIC and system, Fudan University, Shanghai 200433, China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 51-54

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）