ADDLL/VDD-Biasing Co-design for Process Characterization, Performance Calibration, and Clock Synchronization in Variation-Tolerant Designs

摘要：

This work proposes an ADDLL/VDD-biasing co-design methodology for variation-tolerant designs. A modified ADDLL behaves as a variability sensor in the beginning of operation, and the sensing result is used by a VDD-biasing circuit to adjust the VDD of a loaded design for performance calibration. During normal operation, the ADDLL is reused as a de-skewing element for the calibrated design. With this methodology, not only the performance of the loaded design but also that of the ADDLL can be effectively adjusted toward their design specifications even under serious process variations.

作者: Jinn-Shyan Wang Yung-Chen Chien Jia-Hong Lin Chun-Yuan Cheng Ying-Ting Ma Chung-Hsun Huang

作者单位: Department of Electrical Engineering, Chung-Cheng University, Chia-Yi 620, Taiwan

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 55-58

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）