Research on Design of A Reconfigurable Parallel Structure Targeted at LFSR

摘要：

The paper proposed a reconfigurable parallel hardware structure targeted at linear feedback shift register. As to the reconfigurable performance, the structure could reconfigure different LFSR in various stream ciphers. As to the parallel performance, the proposed hardware structure could support parallel .update of LFSR sequences in one clock cycle. Besides, with the tradeoff between the flexibility and high performance, the paper adopted reconfigurable and parallel technology to design a feedback shift register hardware structure, the thesis synthesized the design in 0.18μm CMOS process. The result proves that the critical path of reconfigurable feedback shift register with 256 lengths, random feedback taps, 32 parallelizability is 7.63ns, the throughput rate can achieve 4.09Gbps for LFSR(256 lengths).

作者: Wei Li Xuan Yang Zibin Dai

作者单位: Institute of Electronic Technology, the Information Engineering University, Zhengzhou 450004, China Jiangnan Institute of Computing Technology, Wuxi 214083, China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 67-70

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）