A New Configurable Logic Block with 4/5-input Configurable LUT and Fast/Slow-Path Carry Chain

摘要：

A new LUT and carry structure embedded in the configurable logic block of FPGA is proposed. The LUT is designed to support both 4-input and 5-input structures, which can be configured by users according to their needs without increasing the complexity of interconnect structures. We also develop a new carry chain structure with fast and slow carry paths. The circuit is fabricated in 0.13um 1P8M 1.2/2.5/3.3V Logic CMOS technology. The measured results show a correct function of 4/5-input LUT and a speedup in carry performance of nearly 3 times over current architecture.

关键词： FPGA configurable logic block 4/5-input LUT carry chain optimization

作者: Zhidong Mao Liguang Chen Yuan Wang Jinmei Lai

作者单位: State Key Lab of ASIC and System, Fudan University, Shanghai 201203, P. R. China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 75-78

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）