A 768 Megapixels/sec Inverse Transform With Hybrid Architecture For Multi-Standard Decoder

摘要：

This article introduces a fast hybrid architecture to perform the inverse transform for multiple standards including H.264/AVC, VC-1, MPEG-4, MPEG-2, H.263, and AVS. Both separated and common circuits are used in the hybrid architecture to get high throughput (768 Mpixel/sec for 8-point IDCT and 1536 Mpixel/sec for 4-point IDCT) while keep the area acceptable for many supported standards (56,989 logic gates @ 384 MHz). This hybrid architecture is also very expandable for future codec implementation. The design is described at RTL and synthesized using 130 nm cell library.

关键词： IDCT Inverse Transform Multi-codec Hybrid architecture High throughput Hardware design.

作者: Tuan Minh Phan Ho Thang Minh Le Khanh Duy Vu Seiji Mochizuki Kenichi Iwata Keisuke Matsumoto Hiroshi Ueda

作者单位: Renesas Design Vietnam Company, Ltd, Ho Chi Minh, Vietnam Renesas Electronics Corporation, Tokyo, Japan

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 79-82

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）