A Coarse-grained Reconfigurable Computing Unit

摘要：

This paper presents a 16-bit coarse-grained reconfigurable computing unit. It consists of computing part and interconnection part. The computing part includes adders/subtractors, shifters and complementers, whereas the interconnection part includes multiplexers. Apart from basic functions, it is capable of performing 1-output and 2-output constant multiplication, 4-input adder tree, ·absolute difference and butterfly operation. The implementation results show that the area is 2964 gates with the critical path of 18.24ns under 130-nm CMOS technology.

关键词： Coarse-grained Reconfigurable Computing SCM MCM.

作者: Kanwen Wang Shuai Chen Wei Cao Lingli Wang Jiarong Tong

作者单位: State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 95-98

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）