Double Charge Pump Circuit with Triple Charge Sharing Clock Scheme
A double charge pump circuit with triple charge sharing clock scheme is described. The proposed charge sharing clock generator is able to recover nearly two-thirds of the charge from the parasitics charging, in which way the dynamic power loss in the pumping process is reduced to almost one-third. To preserve the overlapping period of the four-phase clock used for threshold cancellation technique, two complementary sets of clocks are generated from the proposed clock generator, and each set feeds a certain branch of the double charge pump to achieve a between-branch charge sharing. Under 0.18μm technology with a bottom plate parasitic ratio of 0.2, the simulation results of a proposed 5-stage charge pump circuit show an overall efficiency increase with a peak value of 62.8％ comparing to 46.8％ of a conventional one, and the output ripple voltage is reduced by nearly a half.
Mengshu Huang Yimeng Zhang Hao Zhang Tsutomu Yoshihara
Graduate School of Information, Production and Systems, Waseda University Fukuoka, Japan
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
148-152
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）