Design and Verification of an Application-Specific PLD Using VHDL and SystemVerilog
This paper presents a new application-specific PLD architecture which adopts a bit-level.super-systolic array for application-specific arithmetic operation such as MAC. The proposed design offers a significant alternative view on programmable logic device. The bit-level super-systolic array whose cell contains another systolic array is ideal for newly proposed PLD architecture in terms of area efficiency and clock speed as it limits the routing requirement in the PLD to local interconnections between Logic Units and to global interconnections between Logic Modules. The maximum clock cycle is limited only by one AND gate and one full adder. Operations of convolution and FIR filter implemented on the proposed PLD are checked using a System Verilog-coded verification platform.
Jae-Jin Lee Young-Jin Oh Gi-Yong Song
Electrionics and Telecommunications Reaserch Institute, 218 Gajeongno,Yuseong-gu, Deajeon, Korea School of Electronics engineering College of Electrical and Computer Engineering. Chungbuk National
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
183-186
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）