ASIC Implementation of an OFDM Baseband Transceiver for HINOC
This paper describes the implementation of an areaefficient baseband transceiver using a conventional 1.2V, UMC 0.13μm Logic HS FSG process for HINOC communication systems. The novel scheme of channel training (CT) method based on beacon frame is proposed. The chip die size is 5.3 mm × 5:3 mm which fully integrated 2-channels ADC and 2channels DAC. The data throughput in PHY layer achieves 97.44Mbps currently (1024 QAM modulation mode). Total power dissipation is 208.6mW with 3.3V power supply.
HINOC OFDM Baseband QAM
Hongming Chen Xiaoyuan Chen Tie Liu Yuhua Cheng
Shanghai Research Institute of Microelectronics (SHRIME), Peking University, Shanghai, China Shanghai Bwave Technology Co., Ltd Shanghai, China
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
191-194
2011-10-25(万方平台首次上网日期,不代表论文的发表时间)