Design of Four-Transistor Pixel for High Speed CMOS Image

摘要：

This paper designs and tests a series of high speed four-transistor Pixels with 0.13μm CMOS process. The prototype sensor contains 256×128 pixels with 8 different pixel architectures. Pixel size is 10μm×10μm. The measured sensitivity is 17.3V/lux·s, conversion gain is 49.6μV/e-, non-linearity is 3.6％, read noise is 23e-and dynamic range is 60dB. The optimizing design effectively improves the performance of high speed four-transistor Pixel.

作者: Zhou Yangfan Cao Zhongxiang Li Quanliang Qin Qi Wu Nanjian

作者单位: State Key Laboratory for Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 195-198

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）