A Network-on-Chip Simulation Framework for Homogeneous Multi-Processor System-on-Chip

摘要：

This paper presents a Network-on-Chip (NoC) simulation framework at the Electronic System Level (ESL) design abstraction based on SystemC. The proposed ESL NoC framework extends the NIRGAM NoC simulator by integrating ARM Instruction Set Simulator (ISS) as its application Intellectual Property (IP) cores. This enables the modelling of complex homogeneous Multi-Processor System-on-Chip (MPSoC) by simulating the behaviour of embedded cores using ISSs attached to NoC tiles. The actual traffic patterns are extracted according to the target application for NoC performance analysis. In this paper, we describe the development of the extended NoC framework which includes the definitions of synchronization and data communication protocol, interprocess communication module, network interface architecture design, and device driver. Experimental result shows that the extended platform enables early NoC-based MPSoC system functionality estimation and provides NoC performance analysis with higher accuracy by considering the actual traffic trace according to the target application.

关键词： Electronic System Level Homogeneous Multi-processor System-on-Chip Instruction Set Simulator Network- on-Chip Simulation framework SystemC

作者: Yuan Wen Hau M. N. Marsono Chia Yee Ooi M. Khalil-Hani

作者单位: Faculty of Electrical Engineering, Universiti Teknologi Malaysia. 81310 Skudai, Johor. Malaysia

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 199-203

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）