Word Error Control Algorithm through Multi-reading for NAND Flash Memories
This paper presents one * error control scheme for NAND Flash memories with error correction code (ECC). With the increasing array bit error rates, multi bits ECCs like binary Bose-Chaudhuri-Hocquenghem (BCH) code, have been used widely to improve endurance and improve retention. However, with the correction ability and codeword length raise, the parity bits cost increase at the same time. With erasure concept, which means the read data is unstable for erasure cells, this paper proposes a codeword error decrease scheme for NAND Flash memories. This method with no more bits cost could provides more than 70％ error decrease by altering reading data if errors exceed correction capability. It could be combined with BCH code or one-bits ECC like hamming code, for both 1bit/cell or multi-bits/cell memories.
Chong Zhang Tsutomu Yoshihara
Graduate School of Information, Production and Systems, Waseda University, Fukuoka, Japan
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
264-267
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）