A BIST Scheme for High-speed Gain Cell eDRAM

摘要：

A built-in self-test (BIST) scheme is presented for at-speed test of the novel Gain Cell-based embedded DRAM which can operate at the high frequency of 200MHz. This BIST implementation consists of instruction set architecture (ISA) and hardware. A 4stage pipeline for instruction execution makes atspeed test possible. Various kinds of tests, including single-address test, traversal test and refresh test, can be performed by executing different instruction combinations. An 8KB Gain Cell memory with the BIST is fabricated in 0.13μm CMOS technology. Silicon measurement on ATE shows that the BIST can perform at-speed test and measurement types mentioned above.

作者: Bing Yan Yufeng Xie Rui Yuan Yinyin Lin

作者单位: ASIC & System State Key Lab, Dept. of Microelectronics, Fudan University, 825 Zhangheng Rd, 201203, Shanghai, China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 272-275

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）