Single Event Upset Immune Latch Circuit Design Using C-Element
Downscaling trend in CMOS technology on the one hand and reducing supply voltage of the circuits on the other hand, make devices more susceptive to soft errors such as SELL Latch circuits are prone to be affected by SEUs. In this article, we propose a new circuit design of latch using redundancy with the aim of immunity against SEUs. According to simulation results, our design not only guaranties full immunity, but also has the advantage of occupying less area and consuming much less power and performance penalty in comparison with other SEU immune latches. The simulation results show that our solution has 192％ reduction in power and about 103％ reduction in propagation delay in comparison with TMR-latch.
Ramin Rajaei Mahmoud Tabandeh Bizhan Rashidian
Department of Electrical Engineering, Sharif University of Technology, Tehran, IRAN
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
280-283
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）