A Software/Hardware Co-Debug Platform for Multi-Core Systems
In this paper we present a software/hardware co-debug platform to deal with the various debug problems in multiple-core SOC systems with multiple-clock domains. This platform allows designers to debug embedded processors, buses, IP cores, as well as the application programs being developed. It can be used at various design and manufacturing stages including component development, hardware/software co-design, system prototyping, and post-silicon debugging. Three major mechanisms are integrated into this platform, namely a software debug mechanism for multi-core programming, an on-chip hardware debug mechanism for various hardware IPs, and a two-way cross trigger mechanism to synchronize the debug processes of software and hardware. Experimental results on a FPGA prototyping board demonstrate the effectiveness and efficiency of this platform in identifying the root causes of failures for multiple-core SOC systems with multiple-clock domains.
Kuen-Jong Lee Alan Su Long-Feng Chen Jia-Wei Jhou Jiff Kuo Mark Liu
Department of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan Global UniChip Corporation, HsinChu, Taiwan
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
287-290
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）