Word Line Boost and Read SA PMOS Compensation (SAPC) for ROM in 55nm CMOS
This paper presents circuit techniques to improve read capability for single-end SA ROM design fabricated in UMC 55nm process. DVO and DV1 margin are key features reflect read capability, and result show that DVO enhanced significantly by using WL boosting schemes and DV1 enhanced by SA PMOS compensation (SAPC) structure. Combining WL boosting and SAPC technologies, the read fail problem in ROM could be solved easily which bring by leakages especially under 60nm process.
Ruifeng Huang Jianbin Zheng Lijun Zhang Zhaoyong Zhang Hao Wu Yue Yu
Aicestar Technology Corp., Suzhou, China School of Urban Rail Transportation, Soochow University, Suzhou, China
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
335-338
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）