Incremental layout optimization for NoC Designs Based on MILP Formulation

摘要：

Network-on-Chip (NoC) architectures have been proposed as a promising alternative to classic busbased communication architectures. In NoC design, power efficiency is a crucial concern that runs through the whole synthesis process, such as topology generation, mapping, routing, et al. However, it is hard to converge at the final layout generation stage since different stages have different design objects. In this paper, we present an incremental power-aware layout optimization method based on a Mixed Integer Linear Programming (MILP) model at post-layout stage in NoC design. Experimental results show that our optimization flow can achieve 23.3％ power reduction on wires with a reasonable runtime while both the area and chip performance would not compromise.

作者: Jia Liu Yuchun Ma Ning Xu Yu Wang

作者单位: Department of Computer Science and Technology, Tsinghua University, Beijing, China, 100084 School of Department of Computer Science and Technology, Tsinghua University, Beijing, China, 100084 School of Computer Science and Technology, WuHan University of Technology, WuHan, China Department of Electronic Engineering, Tsinghua University,Beijing, China, 100084

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 385-388

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）