Debugging Methodology and Timing Analysis in CDC Solution
As the design complexity of system LSI increasing, the number of clock domains also increases for system LSI designs. Due to the sheer volume of crossing signals and the different ways of crossing implementation, verifying clock domain crossings (CDC) has become a very important yet challenging task. Specialized CDC verification solution needs to be deployed to perform analysis of the design to accurately detect CDC issues as well as efficiently debug the root causes of these problems. This paper describes a case study on CDC verification for FPGA designs using Meridian CDC, Real Intents clock domain crossing verification solution.
Akitoshi Matsuda Jin Zhang
Kyushu Embedded Forum, Fukuoka 8140001, Japan Technical Marketing, Real Intent, Sunnyvale, CA 94043, USA
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
393-396
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）