A New Event Driven Testbench Synthesis Engine for FPGA Emulation

摘要：

FPGA emulation has long provided the highest performance. However, designers have to restrict their coding style or transforming a huge unsynthesizable testbench into synthesizable one by themselves due to usually unsynthesizable testbench. We address this problem by presenting a new event driven testbench synthesis engine called BeEmu (BehaviorLevel Emulator) to translate the behavioral testbench into synthesizable one for FPGA emulation. The proposed testbench synthesis engine is built by hardware constructs in terms of event driven model to correspond with testbench. Experiments demonstrate that our proposed engine can not only have a high simulation speed, but cover more HDL syntax as well.

作者: Haocheng Huang Aiwu Ruan Yongbo Liao Jianhua Zhu Lin Wang Chuanyin Xiang Pin Li

作者单位: State key Laboratory of Electronic Thin Films and Integrated Device, University of Electronic Science & Technology of China, Chengdu 610054, P.R.China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 401-404

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）