Automatic Layout Generator For Embedded FPGA Cores

摘要：

There is a growing tendency for FPGA (Field Programmable Gate Array) IP (Intellectual Property) cores to be embedded in an SOC (System On a Chip). The embedded FPGA cores can improve the flexibility of the SOC chip. However, different SOC varies in the demands on the scale of FPGA tile array.. Therefore, a scalable FPGA generator is required. In this paper, an automatic layout generator to support user-defined FPGA array size is introduced and compared with the previous related works. This paper shows that the proposed layout generator based on FPGA tiles is more practical than the previous tools.

作者: Chaofan Yu Lingli Wang Xuegong Zhou

作者单位: State-Key-Lab of ASIC and System, Fudan University, Shanghai 201203, China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 417-420

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）