An Optimized Mapping Algorithm Based on Simulated Annealing for Regular NoC Architecture

摘要：

Network on chip (NoC) architecture is viewed as a potential solution for the interconnect demands of the emerging multi-core systems since it renders the system high performance, flexibility and low-cost. Mapping tasks onto different cores of the network is a critical phase in NoC design because it determines the energy consumption and packet latency. In order to reduce the energy consumption of applications running on multi-core architecture, we propose a new mapping strategy based on Simulated Annealing (SA). By allocating tasks that have big communication volume to adjacent places on the mesh, the proposed method overcomes the shortcoming of blind search in traditional SA. The experiment results reveal that the solutions generated by the proposed algorithm reduce average energy consumption by 56.56％ in mapping 16 tasks and 66.32％ in mapping 49 tasks compared with traditional Simulated Annealing (SA). 1

关键词： Simulated Annealing mapping NoC multi-core system

作者: Liulin Zhong Jiayi Sheng Minge Jing Zhiyi Yu Xiaoyang Zeng Dian Zhou

作者单位: State Key Laboratory of ASIC & System, Fudan University, Shanghai, China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 421-424

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）