FPGA Interconnect Timing Library Based on the Statistical Method

摘要：

This paper presents a statistical method to build up interconnect timing library of static timing analysis for FPGA design. To overcome a large number of negative values in the traditional interconnect timing library, the statistical method is introduced. The experimental results show that the proposed method could improve the positive ratio and achieve up to 22.35％ on average. Compared to the tested delay results on the FPGA chip, the delay error rate can be reduced from 13.58％ to 11％.

关键词： FPGA Static Timing Analysis statistical method timing library

作者: Xiangzhi Meng Liguang Chen Hao Zhou Jian Wang Meng Yang Jinmei Lai

作者单位: The State Key Lab of ASIC & System, Fudan University, Shanghai 201203, China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 425-428

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）