Latency-Aware Mapping for 3D NoC Using Rank-Based Multi-Objective Genetic Algorithm
Three dimensional network-on-chip (3D NoC) has been suggested as a potential alternative to solve insurmountable problems in 2D field such as global wire length and packet latency for. many years. And the mapping problem plays an import role in 3D NoC design which will have a great influence on overall system performance. In this paper, we mainly focus on the latency-aware mapping for 3D NoC. Differing from the conventional mapping algorithms, the packet latency under no congestion and congestion are both taken into account. Since more than one metrics are considered in this situation, instead of the traditional single-objective genetic algorithm, a rank-based multi-objective genetic algorithm (RMGA) is adopted in our work to explore the optimal approximation of the Pareto-front efficiently and accurately. To evaluate the proposed algorithm, the video object plane decoder (VOPD) is used as a case study. The results show that the RMGA can obtain the approximate Pareto-front well and compared with the best results chosen from random generated solutions, the RMGA can achieve an improvement of 24.4％ and 15.4％ for latency metrics under no congestion and congestion respectively.
Jiawen Wang Li Li Hongbing Pan Shuzhuan He Rong Zhang
Institute of VLSI Design, Nanjing University, Nanjing 210093, China Key Laboratory of Advanced Photonic and Electronic Materials, Nanjing University, Nanjing 210093, China
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
445-448
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）