A matrix approach to low-voltage low-power log-domain CMOS current-mode adjustable-bandwidth step-gain filter design
A novel approach based on state space equation is developed that yields a log-domain CMOS current-mode filter design methodology. Based on this methodology, a practical second-order filter is realized. In the design, most transistors are biased in sub-threshold region. This characteristic leads to the advantages of low voltage and low power. Moreover, the filter has different gain (OdB, -5dB) for the special frequency channel and its bandwidth can be accordingly adapted through the capacitors or the tuning currents. These results demonstrate that the proposed methodology is useful to the current-mode filter design. The second-order filter (1.4 V, 15 μW) is presented in the standard 0.35-μm technology aiming for some extremely low-power and low-voltage applications such as the hearing aid ASIC where the step gain is required to implement. Finally, the high-order filter design through the proposed methodology is also discussed.
Xiaoyu Wang Haigang Yang Tao Yin Fei Liu
Institute of Electronics, Chinese Academy of Sciences, Beijing, China Graduate University of the Chi Institute of Electronics, Chinese Academy of Sciences, Beijing, China
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
481-484
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）