VLSI Implementation of High-Speed Low Power Decimation Filter for LTE Sigma-Delta A/D Converter Application

摘要：

A high-speed low power decimation filter, as a part of a broadband and high resolution sigma-delta A/D converter, is implemented in SMIC 130nm 1P8M CMOS technology. The decimation filter consists of a comb filter and two half-band filters (HBF). Its power consumption is reduced by adopting poly-phase decomposition technique, multiplierless filter architecture and hardware reusage. With a 500MHz sampling frequency, the decimation filter achieves a signal-to-noise ratio of 63.6dB over 20MHz signal bandwidth, while dissipating 4.8mW and occupying an area of 0.12 mm2 .

作者: Jing Li Ran Li Ting Yi Zhiliang Hong Bill Yang Liu

作者单位: State Key-Laboratory of ASIC & Systems, Fudan University, Shanghai 200433, China Analog Devices, Shanghai, China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 489-492

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）