A Time-Domain Flash ADC Immune to Voltage Controlled Delay Line Non-Linearity
A Flash analog-to-digital converter (ADC) architecture operating in time-domain is presented. The proposed ADC uses voltage controlled delay lines (VCDLs) and time-domain comparators instead of preampliflers and voltage-domain comparators in the conventional Flash ADC. Due to the time-domain operation, the proposed Flash ADC benefits from fast switching speed of advanced CMOS process. A key property of the proposed ADC is that its linearity is not affected by the non-linearity of the VCDL, due to the identical VCDLs that are used in both the input signal and reference voltages.
Young-Hwa Kim SeongHwan Cho
Department of Electrical Engineering, KAIST Daejeon, Republic of Korea
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
505-507
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）