A 10-Bit, 50 MS/s, 55 fJ/conversion-step SAR ADC with Split Capacitor Array

摘要：

In this paper, a split capacitor array structure for successive approximation register (SAR) ADC is proposed. By connecting the node of upper plate of LSB capacitor arrays to the reference voltage while MSB operation is activated, the proposed ADC can alleviate the problem of parasitic capacitance without using extra calibration circuitry and conversion cycles. The proposed ADC is designed using 0.13-um 1P6M CMOS technology. At a 1.2-V supply and 50 MS/s, the ADC achieves an SNDR of 56.9 dB and consumes 1.58 mW, resulting in a figure of merit (FOM) of 55 fJ/conversion-step. The ADC core occupies an active area of 350 × 440 um2.

关键词： Analog-to-digital converter (ADC) split capacitor array successive approximation register (SAR) attenuation capacitor.

作者: Seong-Jin Cho Yohan Hong Taegeun Yoo Kwang-Hyun Baek

作者单位: School of Electrical and Electronics Engineering, Chung-Ang University, Seoul, Korea

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 508-511

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）