A 1.8V 100MS/s 10-bit Pipelined Folding A/D Converter With 9.49 ENOB at Nyquist Frequency

摘要：

The design issues of a 10-bit 100MSample/s analog-todigital (A/D) converter with pipelined folding architecture are described. Offset cancellation technique and resistive averaging interpolation network improve the linearity. Cascading alleviates the wide-bandwidth requirement of the folding amplifier. In 0.18μm CMOS technology, the prototype A/D converter achieves 9.49 ENOB, 58.91 dB SNDR and 74.85 dB SFDR at Nyquist frequency input and 100MHz sample clock. The INL and DNL are within ±0.48 LSB and ±0.33 LSB, respectively. The chip occupies 2.29mm2 active area and dissipates 95 mW at 1.8 V power supply.

关键词： A/D converters pipelined folding resistive averaging interpolation offset cancellation

作者: Xiaqjuan Li Yintang Yang Zhangming Zhu

作者单位: School of Microelectronics, Xidian University, Xian 710071, China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 512-515

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）