A sample-and-hold circuit for 10-bit l00MS/s Pipelined ADC
In this paper a fully differential sample-and-hold (S/H) circuit for the pipelined analog-to-digital converter (ADC) was presented. The S/H circuit is based on capacitor flip-around S/H architecture with gain-boosted differential folded cascode operational transconductance amplifier (OTA), which can achieve high DC gain and large bandwidth. Bootstrapped switch and bottom plate sampling techniques are used to reduce the nonlinear distortion. The entire S/H circuit was designed in CSMC 1.8V/3.3V 0.18μm 1P6M CMOS technology. Simulation results show the S/H circuit achieves SNDR of 84dB, ENOB of 13.7, THD of-85dB, and SFDR of 85.4dB at the input frequency 9.86328125M Hz, which is suitable for a 10bit l00MS/s pipelined ADC.
Haitao Wang Hui Hong Lingling Sun Zhiping Yu
Key Laboratory for RF Circuits and Systems of Ministry of Education Hangzhou Dianzi University, Hangzhou 310037, China
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
516-519
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）