A 4-Channel 8-bit 650-MSample/s DAC with Interpolation Filter for Embedded Application
This paper presents a 4-channel 8-bit 6-2 segmented current-steering digital-to-analog converter implemented in 0.13um CMOS process. For the consideration of embedded application two-times interpolation filter with 4 channels parallel inputs is added to the DAC input block. Besides, the DAC system is also optimized for a good high-frequency performance. An improved swing reduction circuit is proposed to decrease the digital signal feed-through to the output. The double centroid current array layout is also used to avoid systemic and graded errors. The measured results show that the DAC achieves over 50dB SFDR at 61MHz input and over 41dB at Nyquist input under a sampling rate of 650MS/s at power consumption of 18mW from a 1.2 V power supply.
Qianqian Ha Fan Ye Chixiao Chen Xiaoshi Zhu Mingshuo Wang ujing Lin Ning Li Junyan Ren
State Key Laboratory of ASIC & System State Key Laboratory of ASIC & System Micro-/Nano-Electronics Science and Technology Innovation Plat
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
528-531
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）