A Multi-mode 1-V DAC+filter in 65-nm CMOS for Reconfigurable (GSM, TD-SCDMA and WCDMA) Transmitters
A 10 bit current-steering DAC and a fourth-order lowpass reconstruction filter are realized in a 65nm CMOS technology to be embedded in multi-standard wireless transmitters. The proposed block meets the specifications of GSM, TD-SCDMA and WCDMA by digitally adjusting the DAC conversion. frequency and the low-pass filter cut-off frequency. As result, the power consumption is optimized according to the operation mode and is 2.8mW in GSM and TD-SCDMA modes, 3.6mW in WCDMA mode. For all considered standards, the SFDR is larger than 75dB, which satisfies all specifications of the standard mentioned above.
Li Li Jun Ma Yawei Guo Xu Cheng Xiaoyang Zeng
State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203, China
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
540-543
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）