Energy efficient ADC design with low voltage operation

摘要：

This paper discusses energy efficient ADC design with low voltage operation. In SAR ADCs, the energy consumption stays constant in the S&H circuit and increases in the comparator with supply voltage, VDD. However, the energy consumed by the logic gates can be reduced using low VDD. Thus, the optimum VDD which minimizes the total energy consumption in SAR ADCs can be found. In flash ADCs, the ENOB is mainly determined by mismatch voltages of the comparators and the energy consumption can be reduced by using lower Vdd; however, it also reduces conversion frequency. Thus, we proposed FoM delay product (FD product) that offers the balance between the energy consumption and conversion speed. The optimum VDD that minimizes FD product can be found. A 0.5 V 5-bit 600 MSps flash ADC has been developed and demonstrated the usefulness of reducing VDD to decrease the energy consumption without serious degradation of the performance.

作者: Akira Matsuzawa

作者单位: Department of Physical Electronics, Tokyo Institute of Technology, S3-27, 2-12-1, O-okayama, Meguro-ku, Tokyo, 152-8552, Japan

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 544-547

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）