CMOS Low-power Subthreshold Reference Voltage Utilizing Self-biased Body Effect

摘要：

Two novel voltage reference using self-biased body effect are discussed in this paper. The proposed circuits based on the weighted difference of two gate-source voltages of two MOSFETs operated in subthreshold region and one of them with forwardbiased body effect, can generate two ultra-low reference voltages of 171.1 mV and 243.2 mV with temperature coefficients of 15.6 ppm/℃ and 14.8 ppm/℃ in a range from -25℃~80℃, respectively. The voltage line sensitivities are 0.0025 ％l and 0.0019％/V. The power supply rejection ratio (PSRR) are -110 dB and -105 dB at 100 Hz. The power dissipations are 0.74 μW and 1.4 μW at a 1.4-V power supply. The circuits were designed and simulated in 0.18 μm CMOS technology. The layouts illustrate the chip area are 0.016 mm2 and 0.014 mm2.

关键词： CMOS voltage reference low power subthreshold body effect area efficient.

作者: Zhang Hao Zhang Yimeng Huang Mengshu Yoshihara Tsutomu

作者单位: Graduate school of Information, Production and Systems, Waseda University, Kitakyushu city 808-0135, Fukuoka, Japan

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 552-555

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）