A Unipolar-CMOS with Recessed Source/Drain Load
In this study, for the first time, we produce a unipolar-CMOS logic, by replacing each of the PMOS devices with a gate-controlled punchthrough NMOS. Such a new logic maintains the traditional advantages of CMOS fabrication while avoiding the need to fabricate large p-well region on chip; this can lead to an improved transistor density, especial in non-Si technologies. To validate the feasibility of this design theory, we use commercial TCAD tools to simulate and verify Unipolar-CMOS inverters, NAND gates, NOR gates, and static random-access memory (SRAM). In each case, the simulation results show that the Unipolar-CMOS logic functions correctly. Moreover, this new logic is scalable to the DecaNanometer range, because the gate-controlled punchthrough NMOS is not significantly affected by the short channel effect. Owing to its superior integration-density and fabrication process, the Unipolar-CMOS technology can not only maintain but also go beyond the Moores law.
Jyi-Tsong Lin Hsuan-Hsu Chen Kuan-Yu Lu Chih-Hung Sun Tung-Yen Lai Fu-Liang Yang
Department of electrical engineering, National Sun Yat Sen University, No.70 Lien-Hai Rd, Kaohsiung National Nano Device Laboratories, Hsinchu 30078, Taiwan
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
579-582
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）