Towards a method for VLSI circuit reverse engineering
This paper tackles the VLSI circuit reverse engineering problem. Actual VLSI circuits are made of several millions of transistors or hundreds of thousands of logical gates. Whether it be for circuit verification, functional abstraction, or simply circuit understanding, reverse engineering aims at building a hierarchy from the transistor level, to gate level, to register level, up to more complex components. The idea is to transform the circuit into a target graph and to look for instances of subcircuits as subgraph patterns in the original graph. In this work, we propose to cast the subgraph isomorphism as a constraint satisfaction problem, where an isomorphism is expressed by a set of constraints and filters.
Hamza Bouchaour Mohammed Ouali Yahia Lebbah
LITIO Lab, B.P. 1524 EL-MNaouar, Oran, 31000, Algeria
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
610-614
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）