Design of 2-3 mixed-valued/six-valued adiabatic asynchronous up-down counter
Through the study of mixed-valued coding, theory, the working principle of adiabatic circuits and up-down counters, a new design of 2-3 mixed-valued/six-valued adiabatic asynchronous up-down counter is proposed. Firstly, the functional expressions of 2-3 mixedvalued /six-valued adiabatic shift right gate and carry/borrow circuit are derived by using the theory of three essential circuit elements, then MOS transistors with different thresholds are adopted to achieve the corresponding structures, and 2-3 mixedvalued /six-valued adiabatic asynchronous up-down counter is further designed on this basis. Finally, HSPICE simulation results verifies correct logic function of the designed circuits, compared with 2-3 mixed-valued /six-valued asynchronous up-down counter, power consumption of the circuits saves up to 94％.
Fengna Mei Pengjun Wang
Institute of Circuits and Systems, Ningbo University, Ningbo 315211, China Institute of Circuits and Systems, Ningbo University, Ningbo 315211, China State Key Laboratory of A
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
619-622
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）