Low Noise Low Power Two-Stage Modulator With Injection Locked LO Divider in 65nm CMOS

摘要：

This paper presents a two-stage modulator for low noise and low power design. The modulator is driven by LO and 2LO; by rejecting noise from the LO path, the modulator achieves a noise floor of -161dBc/Hz at an offset frequency of 40MHz. The modulator also enables the use of a low power injection locked frequency divider (ILFD) to generate quadrature LO. Supplied by 1.2V, the whole circuit consumes only 7.6mA. The modulator is designed in a 65nm CMOS process.

作者: Wufeng Wang Peichen Jiang Tingting Mo Jianjun Zhou

作者单位: Center for Analog/RF Integrated Circuits (CARFIC), School of Microelectronics Shanghai Jiao Tong University, Shanghai 200240, China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 635-638

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）