Design of a Low-Power Low-Phase-Noise Multi-Mode Divider With 25％-Duty-Cycle Outputs in 0.13μm CMOS

摘要：

A high-performance 25％-duty-cycle divider in 0.13μm CMOS for multi-mode wireless communication applications is presented.- Compared with the conventional designs, this work features reduced power consumption and low phase noise by adopting the divide-by-2 divider with intrinsic 25％-duty-cycle outputs. The performance of this work has been demonstrated in a WCDMA/GSM multi-mode multi-band receiver implemented in 0.13μm CMOS.

作者: Song Hu Weinan Li Yumei Huang Zhiliang Hong

作者单位: State Key Laboratory of ASIC & System, Fudan University, Shanghai 201203, China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 639-642

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）