A 0.8ps Minimum-Resolution Sub-Exponent TDC for ADPLL in 0.13μm CMOS

摘要：

This paper presents the design of a sub-exponent time-to-digital converter (TDC) that amplifies a time residue to improve both the time resolution and measurement range. The sub-exponent TDC quantizes the fractional time difference with a cascading chain of 2× time amplifiers. A digitally self-calibrated TA circuit is developed to achieve large input range and stable gain. Simulation results show that implemented in SMIC 0.13μm CMOS, the proposed TDC can achieve a minimum resolution of 0.8ps, a measurement range of 14bits, and a power dissipation of 2mW at 60MHz.

关键词： Time-to-digital converter all-digital PLL time amplifier

作者: Xiaolu Liu Na Yan Xi Tan Hao Min

作者单位: State Key Lab. of ASIC and System, Dept. of Microelectronics, Fudan University Room 365, 825 Road Zhangheng, Shanghai, China 201203

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 651-654

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）