High efficiency and low power multi-rate LDPC decoder design for CMMB

摘要：

High efficiency and low power LDPC decoder for CMMB that supports two rates has been designed in the paper. Layered min-sum algorithm and memory compression technology are adopted to reduce the usage of memory; backup memory method is applied to solve memory read/write conflict existing in CMMB LDPC code at a low cost of memory resource; operational unit multiplexing which can process 1/2 bit rate and 3/4 bit rate simultaneously is used so that the resource consumption of operational unit is reduced. The LDPC decoder designed in this paper is synthesized in the SMC0.18um process. The synthesized result has indicated that the area of designed CMMB LDPC decoder is 7.6mm2 and its power consumption-is 132.8mW.

关键词： low density parity check (LDPC) China mobile multimedia broadcasting (CMMB) decoder FPGA

作者: Jiang xiaobo li hongyuan

作者单位: School of Electronic and linformation Engineering, South China University of Technology, Guangzhou,Guangdong 510641. Chain

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 730-735

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）