Area efficient LDPC decoder design for parallel layered decoding
An area efficient LDPC decoder hardware design for parallel layered decoding algorithm is proposed. Shift register chain is used to reduce the chip area. Puncturing technique is employed to produce arbitrary rate between 1/2 and 1. This design is implemented based on rate-1/2 LDPC in 802.16e with 65nm CMOS. The decoder achieves a throughput of 1.2 Gb/s at 10 iterations with an area of 1.14mm2 and support any rate between 1/2 and 1. Index Terms—LDPC decoder, quasi-cyclic codes, parallel layered decoding algorithm, shift register chain, 802.16e
Yuan Yao Fan Ye Junyan Ren
State Key Laboratory of ASIC and System, Fudan University, 826 Zhangheng Road, Shanghai 201203. China
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
736-739
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）