System Level Performance Evaluation of Three-Dimensional Integrated Circuit

摘要：

Based on a stochastic wire length distributed model, the reduction in the length of interconnects and gate pitch for three-dimensional (3D) integrated circuit is predicted exactly. Using the results of this model, the impact of increasing of the number of active layers on the system performance in term of the product of delay and power dissipation is evaluated. Comparative results with a two-dimensional (2D) integrated circuit show the system performance of 3D circuit with two active layers is improved at least 50％ at sacrifice of 10％ chip temperature, demonstrating 3D integration advantage in future integrated circuit design.

作者: Libo Qian Zhangming Zhu Yintang Yang

作者单位: Microelectronics Institute, Xidian University, Xian 710071, China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 751-754

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）