A JTAG-based Configuration Circuit applied in SerDes Chip

摘要：

In this paper, a design of JTAG-based configuration circuit applied in 2.5 Gbps SerDes (Serializer & Deserializer) mixed digital-analog chip is implemented with SMIC 0.13um technology. The configuration circuit mainly involves two functional components: CR control port and JTAG interface module. The control signals of the whole chip are incorporated in a group of control registers (CRs), which can be accessed through CR control port. The JTAG architecture with 5 standard pins is adopted to load a stream of override data bits into CR port. By applying this combinational configuration methodology, the amount of pinout of the chip has been largely reduced, thus resulting in an efficient saving of chip area. The testing result shows the configuration circuit works perfectly in actual system.

关键词： JTAG CR control port SerDes FPGA

作者: Xun Jiang Xiaoxin Cui Dunshan Yu

作者单位: Institute of Microelectronics, Peking University, Beijing 100871, China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 764-767

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）