A Hardware Accelerator for Speech Recognition Applications

摘要：

A hardware/software co-processing system for speech recognition applications is proposed in this paper. The system consists of a soft-core microprocessor and a dedicated hardware accelerator implemented on an FPGA. This system is intended to be used in embedded devices. By offloading computation-intensive parts of the speech recognition system. to the hardware accelerator, both faster recognition speed and lower power consumption are achieved without degrading recognition accuracy. The design is described in Verilog HDL and synthesized on a Xilinx Virtex-5 FPGA. Tests show that the proposed system runs 2.18 times faster than a pure software system.

关键词： Speech recognition hardware/software co-processing embedded system

作者: Tao Chen Jiawei Zheng Xingsi Zhang Shengchang Cai Yun Chen

作者单位: State Key Lab. of ASIC and System, Fudan University, Shanghai 200433, China

会议类型: 国际会议

会议名称: 2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)

会议地点: 厦门

会议语种:英文

页码: 822-825

在线出版日期: 2011-10-25（万方平台首次上网日期，不代表论文的发表时间）