A Programmable IP Core for LDPC Decoder Based on ASIP
This paper proposes a programmable soft IP core of a LDPC decoder based on ASIP (application-specific instruction set processor) which can support multimode specified in the IEEE802.1 In standard. With the presented specific microinstructions based on ASIP architecture, the decoder can process all the codes for the IEEE802.11n standard in a programmable approach, effectively, and due to the proposed 6stage pipeline, the decoder performance is improved greatly. To verify the design, the IP has been integrated into a embedded processor system based on Xilinx EDK on a Xilinx Virtex5 FPGA component. Finally, the Logic synthesis on 0.18μm CMOS technology from UMC reveals a maximum clock frequency of 203MHz and a total area of 3.94mm2, and the corresponding power consumption is below 326.49mW.
Jun Deng Bing Li Lintao Liu Rui Chen
Sichuan Institute of Solid-state Circuits, Chongqing, 400060, China School of integrated circuits, Southeast University, Nanjing, 210096, China Science and Technology on Analog Integrated Circuit Laboratory, Chongqing, 400060. China
国际会议
2011 IEEE 9th International Conference on ASIC(2011年第九届IEEE国际专用集成电路大会)
厦门
英文
826-829
2011-10-25（万方平台首次上网日期，不代表论文的发表时间）